1. Field of the Invention
The present invention relates to semiconductor packaging technology and, more particularly, to a semiconductor package having leads and a stack structure of this package.
2. Description of the Related Art
As is well known in the art, semiconductor integrated circuit chips such as memory chips are assembled in packages. The package is mounted on substrates of various electronic components. In order to electrically connect and mechanically attach the packages to a substrate, a lead frame is generally used. FIG. 1 shows a conventional semiconductor package using the lead frame.
As shown in FIG. 1, a semiconductor package 1 comprises two semiconductor integrated circuit chips 2 attached to upper and lower surfaces of a die pad 3 to increase memory capacity. A lead frame comprises the die pad 3 on the center and a plurality of leads 4 disposed around the die pad 3. The die pad 3 mechanically supports the chips 2. The leads 4 electrically connect the semiconductor chips 2 to the substrate 10. The semiconductor chips 2 are electrically connected to the leads 4 by bonding wires 5. The semiconductor chips 2 and the bonding wires 5 are encapsulated with a molding resin such as epoxy molding compound, thereby forming a molding part 6. Outer portions of the leads 4, i.e., outer leads, which are exposed and extend from the molding part 6, are bent in predetermined shapes to be suitably mounted on the substrate 10, and the package 1 is mounted on the substrate 10.
In order to operate the chips 2 on the substrate 10, the conventional package 1 requires a large mounting area and mounting height. As shown in FIG. 1, compared to the dimension and the thickness of the chip 2 itself, the mounting area xe2x80x9caxe2x80x9d and the mounting height xe2x80x9chxe2x80x9d of the package 1 are excessive. Thus, with this conventional package, it has been difficult to satisfy the pressing demand for smaller and thinner packages. Further, the length of the leads 4 of the package 1 causes signal delay during the chip operation and reduces mounting reliability.
In accordance with one embodiment of the present invention, a semiconductor package, in which the lower surfaces of leads are partially exposed from a molding part, is provided. The semiconductor package may include a lead frame having a die pad in the center and a plurality of leads disposed around the die pad. The package comprises at least one semiconductor integrated circuit chip attached to the die pad. The lead frame and the chip are encapsulated within the molding part. The molding part includes an upper molding portion having a first width and a lower molding portion having a width smaller than the first width, thereby partially exposing the lower surfaces of the leads from the molding part.
In another embodiment, a mounting structure for the above-described package on a substrate is provided. In this mounting structure, the substrate has a cavity for receiving the lower molding portion of the package. The exposed lower surfaces of the leads may be attached to the substrate with a conductive adhesive.
In an alternative embodiment, the present invention provides a stack structure for stacking at least two of the above-described packages. In each package, projections are formed on the upper molding portion and recesses are formed on the lower molding portion. Each of the projections corresponds to one of the recesses in position and shape. The leads extend from a side surface of the upper molding portion and bent toward the upper molding portion of the package. The packages are stacked by engaging the projections of a lower package with the recesses of an upper package stacks the packages, and the bent parts of the package leads are connected with a conductive adhesive.
With the present invention, the mounting area and the mounting height of a package on a substrate can be reduce. Also, the mounting reliability of a package on a substrate and electrical characteristics of the package can be improved.